Fundamentals of Processor Architecture and SoC Design

VL326 is a core course on how a processor is designed and how it works with the memory system in a modern System-on-Chip (SoC). It starts from logic gates and flip-flops and ends with a pipelined RISC-V processor and its memory hierarchy. Throughout, the course connects the instruction set, which is the contract between hardware and software, to the circuits that implement it, and uses numbers to compare design trade-offs in speed, cost and energy.

Course outline

• Unit 1 - Foundations of Computer Organization: organization versus architecture, von Neumann and Harvard machines, the levels of a digital system from device to SoC, combinational and sequential (FSM) design, RTL building blocks and programmable logic (ROM, PLA, PAL, FPGA and the Zynq SoC), CPU performance (CPI, MIPS and the Amdahl law), IEEE 754 floating-point arithmetic, instruction set design (stack, accumulator and load-store machines, RISC versus CISC, addressing modes, the semantic gap), the RISC-V RV32I ISA, and an introduction to computability and complexity.
• Unit 2 - Single-Cycle CPU: hardware elements of a CPU, the five steps of instruction execution, building a complete single-cycle RISC-V datapath, hardwired control and ALU control, timing and the critical path, and a worked example that takes a factorial program from C to RISC-V machine code.
• Unit 3 - Multicycle and Pipelined CPU: multicycle microarchitecture and microprogrammed control, pipelining principles and cost, the five-stage RISC-V pipeline, data hazards with stalling and forwarding, control hazards with predication and delayed branching, fine-grained multithreading, and branch prediction with BTBs, static schemes and 1-bit and 2-bit dynamic predictors.
• Unit 4 - Memory Subsystems: the memory hierarchy and locality of reference, SRAM and DRAM technology, cache design (direct-mapped, set-associative and fully associative caches, replacement and write policies, multi-level caches, the 3C miss classification), DRAM organization, timing and address mapping, and virtual memory with paging, page tables, TLBs and protection.

Learning outcomes

By the end of the course, students will be able to:

• explain how high-level code is executed by hardware, from the ISA down to gates
• design and analyse combinational and sequential circuits and simple datapaths
• represent numbers in IEEE 754 and work through floating-point arithmetic by hand
• encode and decode RISC-V instructions and trace them through single-cycle, multicycle and pipelined datapaths
• identify pipeline hazards and evaluate stalling, forwarding and branch prediction
• calculate CPI, execution time, AMAT and cache and DRAM parameters to compare design choices
• describe how caches, DRAM and virtual memory together give the illusion of a large, fast memory

Course materials

Lecture slides plus four unit handbooks with detailed figures, worked numerical examples, advanced topics and exercises with answers. The hands-on component uses RISC-V and FPGA platforms (Zynq ZedBoard).

Prerequisites: digital logic design and basic programming in C.