Software & resources · Software release
Digital Logic Synthesis Tool v1.0
A²DSL has released the Digital Logic Synthesis Tool, a hands-on toolkit for learning how synthesis tools minimize and optimize digital circuits.
With a single command, users can minimize finite state machines, compare state encodings, run two-level minimization with espresso, and explore multi-level optimization (factoring, kernels and extraction) using the classic Berkeley SIS tools. Every result is explained step by step, problems are written in plain textbook notation, and generators create larger examples for exploration.
The kit was developed for the course VL-401 RTL Design and Verification at IIT Mandi and is open to everyone for educational and research use. It runs on Linux with Python 3 and nothing to install, and on Windows through WSL or a Google Colab notebook.
Downloads & documentation · 2
Guide
- Digital Logic Synthesis Tool Guide PDF · 167 KB View Download
Main Tool
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Logic Synthesis
ZIP · 4.3 MB
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