[12]
XSC: A Correlation-Aware Stochastic Computing Extension for RISC-V Edge Processors.
Conference Paper
People / B.Tech Student
Om Maheshwari
Btech Scholar (2023 - 2027)
- b23089@students.iitmandi.ac.in
- Phone
- 8859141410
Research interests
Computer Architecture
Computer architecture and VLSI undergraduate specializing in RISC-V custom ISA extension design, microarchitecture and memory-subsystem simulation (gem5, Spike, QEMU), RTL design, ASIC synthesis, and FPGA prototyping. Various peer-reviewed IEEE publications, one granted patent, and five patent applications spanning ISA design, cache management, and low-power architecture.
Publications
2027
[11]
QIEDP-X: Reliability-Guided Collision Resolution for Short-Block IoT Serial Links
Conference Paper
2026
[10]
TILY: A CONFIGURABLE TILE-BASED HETEROGENEOUS RISC-V SOC PLATFORM
Thesis
PDF
[9]
BAYESIAN CONFIDENCE-BASED MEMORY DEPENDENCE PREDICTOR SYSTEM AND METHOD FOR TUNABLE SPECULATIVE LOAD
Patent
[8]
BIO-INSPIRED ADAPTIVE DYNAMIC PRECISION SCALING SYSTEM FOR IEEE 754 FLOATING-POINT UNITS
Patent
[7]
PROCESSOR ARCHITECTURE WITH COMPRESSION AND DECOMPRESSION EXTENSION CIRCUITRY FOR IN-PIPELINE DATA PROCESSING
Patent
[6]
A SYSTEM FOR ANOMALY DETECTION AND METHOD THEREOF
Patent
[5]
NEUROMORPHIC ADAPTIVE PRECISION RISC-V PROCESSOR FOR DYNAMIC PRECISION SCALING AND METHOD THEREOF
Patent
[4]
TWO-BIT ERROR DETECTION AND CORRECTION IN DATA TRANSMISSION BY QUANTUM-INSPIRED ERROR DETECTION PROTOCOL (QIEDP)
Patent
PDF
[3]
2025
[2]
[1]